1. Field of the Invention
The present invention relates to a memory testing apparatus for testing various kinds of semiconductor memories including a memory being constructed by, for example, a semiconductor integrated circuit (hereinafter, referred to as IC) and a method of analyzing a relief or repair of failure cell or cells in a memory, which includes the steps of counting the number of failure memory cells of a semiconductor memory tested by this memory testing apparatus and determining whether or not a repair of the tested semiconductor memory is possible. (Hereinafter, a memory being constructed by a semiconductor integrated circuit is referred to as IC memory.) More particularly, the present invention relates to a method of analyzing a repair of failure cell or cells in a memory, which includes the step of determining whether or not a repair of failure called in this technical field xe2x80x9cmust-repairxe2x80x9d in a memory of redundancy structure can be carried out and a memory testing apparatus having a failure relief analyzer using this analyzing method.
2. Description of the Related Art
In recent years, increase of memory capacity and miniaturization of an IC memory have been attempted. Associated with the increased memory capacity and the miniaturization of an IC memory, defect rates of IC memories have been increased. In order to decrease the defect rates, in other words, in order to prevent the yield from being decreased, there have been manufactured, for example, IC memories in each of which failure memory cells can be electrically replaced with spare memory cells (referred to as spare lines, relief lines or a redundancy circuit in this technical field). The IC memories of this type each having spare memory cells are called, in this technical field, memories having redundancy structure, and the determination as to whether or not a relief of failure memory cells of a memory having redundancy structure is possible is performed by a failure relief analyzer. Recently, storage capacity of an IC memory is increasing more and more, and accordingly an increased IC chip area and formation of patterns at high density are required. As a result, there is an increased possibility that a reduction of the yield of IC memories caused by a very minute defect occurs. In order to prevent the yield of IC memories from being reduced, there are manufactured IC memories in each of which, for example, one or more failure memory cells can be electrically replaced by a substitute or alternative memory cell (also called a spare line, relief line or redundancy circuit). As will be described later, the IC memory of this kind is called a memory of redundancy structure in this technical field, and a decision as to whether the redundancy-structured memory can be relieved or not is rendered by a failure relief analyzer.
FIG. 5 is a block diagram showing a schematic configuration of an example of a memory testing apparatus having a conventional failure relief analyzer. This memory testing apparatus TES comprises, roughly speaking, a main controller 111, a pattern generator 112, a timing generator 113, a waveform formatter 114, a logical comparator 115, a driver 116, an analog level comparator (hereinafter referred to as a comparator) 117, a failure analysis memory 118, a failure relief analyzer 120, a logical amplitude reference voltage source 121, a comparison reference voltage source 122 and a device power source 123. Further, in the following description, a case of testing an IC memory will be described. However, various semiconductor memories other than IC memories are similarly tested.
The main controller 111 is generally constituted by a computer system in which a test program PM created by a user (programmer) is loaded in advance, and the control of the entire memory testing apparatus is performed in accordance with the test program PM. This main controller 111 is connected, via a tester bus BUS, to the pattern generator 112, the timing generator 113, the failure analysis memory 118, the failure relief analyzer 120 and the like. Although not shown, the logical amplitude reference voltage source 121, the comparison reference voltage source 122 and the device power source 123 are also connected to the main controller 111.
An IC memory to be tested (IC memory under test, generally referred to as MUT) 119 is mounted on a socket of a test head (not shown) constructed separately from the memory testing apparatus proper. Usually, a member called a performance board is mounted on the upper portion of the test head, and a predetermined number of IC sockets are mounted on the performance board. Therefore, the IC memory under test 119 is mounted on related one of the IC sockets. In addition, a printed-circuit board called pin card in this technical field is accommodated inside the test head. Usually, a circuit containing the driver 116 and the comparator 117 of the memory testing apparatus TES is formed on this pin card. In general, the test head is mounted on a test section of an IC transporting and processing apparatus called handler in this technical field, and is electrically connected to the memory testing apparatus proper by signal transmission means such as a cable, an optical fiber or the like.
First of all, before starting the test of the IC memory, various kinds of data are set by the main controller 111. After the various kinds of data have been set, the test of the IC memory is started. When the main controller 111 issues a test starting command to the pattern generator 112, the pattern generator 112 starts to generate a pattern. The pattern generator 112 supplies a test pattern data to the waveform formatter 114 in accordance with the test program PM. On the other hand, the timing generator 113 generates a timing signal (clock pulses) for controlling operation timings of the waveform formatter 114, the logical comparator 115 and the like.
The waveform formatter 114 converts the test pattern data supplied from the pattern generator 112 into a test pattern signal having a real waveform. This test pattern signal is applied to the IC memory under test (hereinafter referred to as memory under test) 119 via the driver 116 that amplifies the voltage of the test pattern signal to a waveform having an amplitude value set by the logical amplitude reference voltage source 121. The test pattern signal is stored in a memory cell of the memory under test 119 having an address specified by an address signal, and the storage content is read out therefrom during a read cycle later on.
A response signal read out from the memory under test 119 is compared with a reference voltage supplied from the comparison reference voltage source 122 in the comparator 117, and it is determined whether or not the response signal has a predetermined logical level, i.e., whether or not the response signal has a predetermined logical H (logical high) voltage or logical L (logical low) voltage. A response signal determined to have the predetermined logical level is sent to the logical comparator 115, where the response signal is compared with an expected value pattern signal, and whether or not the memory under test 119 has outputted a normal response signal is determined.
If the response signal is not equal to the expected value pattern signal, a memory cell having an address of the memory under test 119 from which the response signal was read out is determined to be in failure, and a failure signal indicating the failure is generated from the logical comparator 115. Usually, when a failure signal is generated, a writing of a failure data (generally logical xe2x80x9c1xe2x80x9d signal) applied to a data input terminal of the failure analysis memory 118 is enabled, and the failure data is stored in an address of the failure analysis memory 118 specified by an address signal being supplied to the failure analysis memory 118 at that time.
The failure analysis memory 118 has an operation speed and a memory capacity equivalent to those of the memory under test 119. An address signal that is same as the address signal applied to the memory under test 119 is applied to this failure analysis memory 118. In addition, the failure analysis memory 118 is initialized prior to starting the test. For example, a data of xe2x80x9c0xe2x80x9d is written, by the initialization, in each of all the addresses of the failure analysis memory 118. Every time a failure signal indicating a discordance between the response signal and the expected value pattern signal is generated from the logical comparator 115 in the test of the memory under test 119, a failure data of logical xe2x80x9c1xe2x80x9d indicating a memory cell failure is written in the same address of the failure analysis memory 118 as that of the memory cell of the memory under test 119 in which the discordance is detected.
On the contrary, when the response signal is equal to the expected value pattern signal, a memory cell of the address of the memory under test 119 from which the response signal was read out is determined to be normal, and a pass signal indicating the normal memory cell is generated. This pass signal is not usually stored in the failure analysis memory 118.
At the time point when the test is completed, the failure data stored in the failure analysis memory 118 are read out therefrom into the failure relief analyzer 120, and it is determined whether or not a relief of failure memory cells of the tested IC memory 119 is possible.
The failure relief analyzer 120 simultaneously and separately counts the total number of failure memory cells and the number of failure memory cells on each of row address lines and column address lines stored in the failure analysis memory 118, and analyzes Whether or not those failure memory cells can be relieved by the spare lines provided for each of a plurality of storage areas (memory cell array) of the memory under test 119.
Further, in FIG. 5, the block diagram is depicted such that the test pattern signal outputted from the driver 116 is applied to only one input terminal of the memory under test 119, and a response signal from one output terminal of the memory under test 119 is supplied to the comparator 117. However, the number of drivers 116 provided is actually equal to the number of input terminals of the memory under test 119, for example 512, and the number of comparators 117 provided is also equal to the number of output terminals of the memory under test 119 (since the number of input terminals provided is usually equal to the number of output terminals, the number of comparators 117 provided is equal to the number of drivers 116 provided). In addition, although the input terminals of the memory under test 119 are depicted, in FIG. 5, as separate terminals from the output terminals of the memory under test 119, there are many cases in general where each terminal of the memory under test 119 is commonly used for both input terminal and output terminal. Moreover, although each of the elements (the main controller 111, the pattern generator 112, the timing generator 113, the waveform formatter 114, the logical comparator 115, the failure analysis memory 118, the failure relief analyzer 120 and the like) except for the driver 116 and the comparator 117 is represented by one block, there are also actually provided in each block the same number of elements as that of the drivers 116 (for example, 512) except for the main controller 111 and the timing generator 112. That is, only the main controller 111 and the timing generator 112 are commonly used for the terminals of the memory under test 119.
FIG. 6 shows the internal structure of the memory under test 119. An IC memory constituted by a semiconductor integrated circuit has a plurality of storage areas 2 formed on the same semiconductor chip 1. Each storage area 2 is constituted by many memory cells aligned along row address lines and column address lines, and is called a memory cell array (MCA) in this technical field. A memory element having desired storage capacity is constituted by the plurality of storage areas 2. In addition, each of the plurality of storage areas 2 is selectively accessed by a storage area (block) address signal that is to be described later on.
As shown in FIG. 7 in enlarged form, each storage area 2 has a memory cell array MCA in which memory cells have been arrayed in a matrix manner of rows and columns, and in addition to the memory cell array MCA, is provided with a desired number of row spare lines SR and a desired number of column spare lines SC formed in the row address direction ROW and in the column address direction COL along the periphery of the memory cell array MCA, respectively. These spare lines SR and SC are provided for the purpose of relieving failure memory cells, and serve to change a memory under test that has been determined to be a defective or failure article to a non-defective or pass article by electrically replacing the detected failure memory cells in the storage area 2 with those spare lines. Further, in this example, a case is shown where two row spare lines SR are disposed along one side of the row address direction of the memory cell array MCA and two column spare lines SC are disposed along one side of the column address direction of the memory cell array MCA, respectively. However, it is needless to say that the number of spare lines and the positions where these spare lines are disposed are not limited to the example as illustrated.
The number of failure memory cells that can be relieved by the spare lines orthogonal to address line directions in the storage area 2 is restricted by the number of the spare lines SR formed in the row address direction ROW and the number of spare lines SC formed in the column address direction COL. For this reason, after the test is completed, at first the number of failure memory cells is obtained for each storage area 2, and row address lines and column address lines on which these failure memory cells are present are located for each storage area 2 to determine whether or not those failure memory cells on those address lines can be relieved by the spare lines orthogonal to their respective address lines.
The failure relief analyzer 120 includes, as shown in FIG. 8, a row address failure number counter/memory RFC for counting and storing therein the number of failure memory cells present on each of the row address lines in each storage area 2, a column address failure number counter/memory CFC for counting and storing therein the number of failure memory cells present on each of the column address lines in each storage area 2, and a total failure number counter/memory TFC for counting and storing therein the total number of failure memory cells in each storage area 2. Further, the row address failure number counter/memory RFC and the column address failure number counter/memory CFC are constructed in reality such that those counters/memories RFC and CFC count the number of failure data read out from the failure analysis memory 118 each representing a failure memory cell in each of the row address line and column address line, respectively, and the counted values are stored in their respective failure storing memories. The total failure number counter/memory TFC is constructed such that the total failure number counter/memory TFC accumulates, each time a failure data is read out from the failure analysis memory 118, the number of failure occurrences, and the accumulated value is stored in the total failure storing memory of the total failure number counter/memory TFC.
As an occurrence state of failure memory cells, there is a case in which, as shown in FIG. 9, many failure cells FC are present on one row address line RLN or on one column address line CLN. A state that the number of failure memory cells FC on one address line is larger than the number of spare lines provided in the direction orthogonal to their address line RLN or CLN is generally called a must-repair MS in this technical field. This must-repair MS cannot be repaired by the spare lines provided in the direction orthogonal to its address line RLN or CLN. Therefore, it is necessary to relieve such a must-repair using a spare line SR or SC that is provided in parallel to the must-repair address line RLN or CNL. As a failure relief analyzing procedure, the must-repair MS must be first detected. Then, the spare line used for the repair of the must-repair MS and the repaired failure memory cells are excluded from the consideration for further failure relief, and thereafter it is determined whether or not the remaining failure memory cells can be relieved by the remaining spare lines.
A must-repair MS is searched in both row address direction ROW and column address direction COL. Specifically explaining, first, when the storage content of the row address failure number counter/memory RFC is read out in the row address sequence, the number of failure memory cells present on each row address line of each storage area 2 can be read out. The number X1 of failure memory cells stored in each of the row addresses is compared with the number Y1 of column spare lines SC. If the comparison result is X1 greater than Y1, the row address line is determined to be in must-repair state. The row address determined to be in must-repair state is sent to the main controller 111, and is stored in the main controller 111 as a row must-repair address.
Next, the storage content of the column address failure number counter/memory CFC is read out in the column address sequence to read out the number of failure memory cells present on each column address line of each storage area 2. The number X2 of failure memory cells stored in each of the column addresses is compared with the number Y2 of row spare lines SR. If the comparison result is X2 greater than Y2, the column address line is determined to be in must-repair state. The column address determined to be in must-repair state is sent to the main controller 111, and is stored in the main controller 111 as a column must-repair address.
When the searching operation of must-repair addresses has been completed, the main controller 111 sets the stored row and column must-repair addresses in the failure relief analyzer 120, and makes the failure relief analyzer 120 perform a data updating operation. A must-repair MS cannot be repaired unless one spare line that is in parallel with the must-repair address line is used. Therefore, if a must-repair MS is present only on one row address line RLN, for example, one row spare line SR must be used. As a result, if a must-repair MS is present only on one row address line RLN, there is performed an operation of decreasing the number of row address lines SR by one as well as subtracting the number of failure memory cells on the row address line on which the must-repair MS is present from each of the row address failure number counter/memory RFC, column address failure number counter/memory CFC and the total failure number counter/memory TFC. By this operation, the memory under test 119 will be repaired to a non-defective article for the present.
Even if only one must-repair address is present on one of row addresses, the number of row spare lines is decreased by one. Therefore, the number of row spare lines SR is changed. As a result, regarding column address lines that are orthogonal to the row spare line SR, a searching operation for a must-repair must be performed again with respect to the changed number of row spare lines SR. The search condition in this case is to compare the number X2 of failure memory cells of each column address with Y2xe2x88x921 that is a number resulted by subtracting one (1) from the number Y2 of row spare lines SR. If the comparison result X2 greater than Y2xe2x88x921 is detected, the corresponding column address is sent to the main controller 111 as a column must-repair address, and is stored therein.
When the searching operation of must-repair addresses in the column address direction COL is completed, the main controller 111 sets again the column must-repair addresses detected with respect to column addresses in the failure relief analyzer 120, and makes the failure relief analyzer 120 perform a data updating operation. If, for example, a must-repair MS is present only on a column address line CLN, it is deemed that one column spare line SC has been used, and 1 is subtracted form the number of column spare lines SC. Moreover, the number of failure memory cells on the column address line on which the must-repair MS is present is subtracted from each of the row address failure number counter/memory RFC, column address failure number counter/memory CFC and the total failure number counter/memory TFC. By this operation, the memory under test 119 is changed to a non-defect article again.
Since the number of column spare lines SC is decreased by one by this updating operation, a searching operation for a must-repair must be performed again this time with respect to row address lines that are orthogonal to the column spare line SC. In this manner, the searching operation of a must-repair and the updating operation of the analysis data are repeated until any must-repair is not detected.
As mentioned above, in the prior art system, the failure relief analyzer 120 operates under control of the main controller 111. Therefore, the main controller 111 sets first in the failure relief analyzer 120 a storage area to be relieved and the numbers of row spare lines SR and column spare lines SC, and then makes the failure relief analyzer 120 continuously perform the must-repair searching operation for the set storage area until the last addresses in the row address direction ROW and the column address direction COL are generated. When the failure relief analyzer 120 detects a must-repair, the main controller 111 stores therein its address. Upon completion of the must-repair searching operation by the failure relief analyzer 120 with respect to the row address direction and the column address direction, the main controller 111 updates analysis data set in the failure relief analyzer 120. Then the main controller 111 makes the failure relief analyzer 120 perform again the must-repair searching operation based on the updated analysis data. After that, whenever a must-repair is detected, the main controller 111 makes the failure relief analyzer 120 perform the must-repair operation with respect to the other address direction that is different from the address direction of the detected must-repair (if the address of the detected must-repair is a row address, the other address direction is the column address direction). This must-repair searching operation is performed until any must-repair is not detected.
For this reason, the main controller 111 repeats many times the operations of setting the storage areas to be relieved and the numbers of row and column spare lines SR and SC, acquiring must-repair addresses, and reading out the acquired must-repair addresses to set them in the failure relief analyzer 120 and to update the number of spare lines SR and SC. In addition, the failure relief analyzer 120 repeats many times the must-repair searching operation and the operation of subtracting the number of failure memory cells on the address line on which the must-repair is present from the row address failure number counter/memory RFC, the column address failure number counter/memory CFC and the total failure number counter/memory TFC. In this manner, the acquiring and reading operations of the must-repair addresses, the setting and updating operations of analysis data, and the subtracting operations of the numbers of failures are repeated many times, and hence it takes long time for those operations. As a result, there is a disadvantage in the prior art system that it takes, as a whole, a long time for the must-repair searching operations.
In addition, in the prior art system, at least one must-repair searching operation must be performed with respect to row address direction ROW and column address direction COL for the storage area 2 where there is no failure memory cell. This fact is also one of factors of taking long time in the failure relief analysis.
In recent years, there has been a tendency that the storage capacity of a memory under test is increasing, and the number of storage areas to be relieved and the area of each of the storage areas are increased. Therefore, the must-repair searching time has increased more and more. For this reason, there is a drawback in the prior art system that the test time of an IC memory is long.
It is a first object of the present invention to provide a method of analyzing a relief of failure cells in a memory, which is capable of completing a failure relief analysis in a short time even if a memory under test has many storage areas.
It is a second object of the present invention to provide a memory testing apparatus having a failure relief analyzer using the above method of analyzing a relief of failure cells.
It is a third object of the present invention to provide a method of analyzing a relief of failure cells in a memory, which is capable of completing in a short time a must-repair address searching operation and an updating operation of data due to the repair of a must-repair.
It is a fourth object of the present invention to provide a memory testing apparatus having a failure relief analyzer using the method of analyzing a relief of failure cells described in the above third object of the present invention.
In order to accomplish the aforesaid objects, there is provided, in one aspect of the present invention, a method of analyzing a repair of failure cell in a memory comprising the steps of: testing a memory having a plurality of storage areas; detecting whether or not the number of failure memory cell on a row or column address line of each of the storage areas is greater than the number of spare line for relieving a failure, said spare line being provided in orthogonal direction to said row or column address line; determining, when the number of failure memory cell is greater than the number of spare line, the failure memory cell to be xe2x80x9cmust-repairxe2x80x9d; and assuming that the failure memory cell on the address line determined to be the xe2x80x9cmust-repairxe2x80x9d has been repaired by use of the spare line and updating data in such state that said xe2x80x9cmust-repairxe2x80x9d has been repaired, said method further comprising the steps of: carrying out, each time a xe2x80x9cmust-repairxe2x80x9d is detected on a row address or column address, an updating process of said data at the position of the row address or column address from which the xe2x80x9cmust-repairxe2x80x9d has been detected; and continuing to search a xe2x80x9cmust-repairxe2x80x9d after the updating process of the data has completed.
In another aspect of the present invention, there is provided a memory testing apparatus for testing a memory having a plurality of storage areas and at least one spare line for relieving a failure provided on each of said storage areas, said apparatus having a failure relief analyzer for counting, each storage area, the total number of failure memory cells, the number of failure memory cell on each row address, and the number of failure memory cell on each column address, respectively, and analyzing a method of repairing the failure memory cells for each storage area, and comprising: an analyzed storage area detector for searching whether a failure memory cell exists or not on each storage area and determining whether a failure relief analysis for the storage area should be carried out or not; a memory for storing the number of spare lines, said memory storing the number of spare line provided in row address direction and the number of spare line provided in column address direction of each storage area, respectively; a must-repair searching-apparatus for comparing the number of spare line stored in said number of spare line storing memory with the number of failure memory cell on a row address line or column address line of each storage area, detecting a state that the number of failure memory cell is greater than the number of spare line provided in orthogonal direction to the address line and determining the detected state to be a must-repair; data updating apparatus for carrying out, each time said must-repair searching apparatus detects a must-repair, a process of updating data to such state that failure memory cells on the address line of the detected must-repair have been repaired by use of the spare line; a re-starting apparatus for detecting the end of the data updating process carried out by said data updating apparatus and re-starting said must-repair searching apparatus; must-repair search resuming means detecting the fact that said data updating apparatus has operated and causing a search of must-repair to be resumed, under the condition that the number of updated spare line by the simulation process of the data updating apparatus is used in detecting a must-repair; and search ending means detecting the fact that no must-repair is detected during the search of a must-repair and ending the search of a must-repair for the storage area being analyzed.
In a preferred embodiment, the aforesaid analyzed storage area detector comprises: a storage area address generator for generating addresses given to said plurality of storage areas; a total failure number counter/memory for storing the total number of failure memory cells for each storage area, said total failure number counter/memory being accessed by a storage area address signal outputted from said storage area address generator and outputting the total number of failure memory cells of the corresponding storage area; zero detecting means detecting the fact that the total number of failure memory cells read out of said total failure number counter/memory is xe2x80x9c0xe2x80x9d; means incrementing the address outputted from said storage area address generator each time said zero detecting means detects xe2x80x9c0xe2x80x9d; and means starting said must-repair searching apparatus in case that the total number of failure memory cells read out of said total failure number counter/memory is a numerical value other than xe2x80x9c0xe2x80x9d.
The aforesaid spare line number storing memory comprises: a memory for storing the number of spare line provided in the row address direction; and a memory for storing the number of spare line provided in the column address direction, said memories being accessed by a storage area address signal outputted from said storage area address generator and outputting the number of spare line prepared on the corresponding storage area, respectively.
The aforesaid must-repair searching apparatus comprises: a row address failure number counter/memory for storing the number of failure memory cells on each row address line for each storage area; a column address failure number counter/memory for storing the number of failure memory cells on each column address line for each storage area; a row address generator for accessing said row address failure number counter/memory; a column address generator for accessing said column address failure number counter/memory; a first comparator for comparing the number of failure memory cells on each row address line read out of said row address failure number counter/memory with the number of spare line provided in orthogonal direction to the row address line and detecting a must-repair on the row address line; and a second comparator for comparing the number of failure memory cells on each column address line read out of said column address failure number counter/memory with the number of spare line provided in orthogonal direction to the column address line and detecting a must-repair on the column address line.
The aforesaid data updating apparatus comprises: a controller for performing a control which prevents said row address generator or column address generator under incrementing operation from doing the incrementing operation, and a control which increments said column address generator or row address generator having paused in operation from the first address to the last address, during a search of a must-repair by a detection signal that said must-repair searching apparatus has detected either one of a must-repair on a row address line or a must-repair on a column address line; a first subtracter for updating the number of spare line by assuming that one spare line has been used for relieving the detected must-repair and setting the updated number of spare line in said memory for storing the number of spare lines; a second subtracter for performing a subtraction of xe2x80x9c1xe2x80x9d from the total number of failure memory cells of the corresponding storage area outputted from said total failure number counter/memory each time a failure memory cell is read out from said row address failure number counter/memory or column address failure number counter/memory read out by the incrementing operation of said row address generator or column address generator which has started to do its incrementing operation, and setting the result of the subtraction in said total failure number counter/memory; and third and fourth subtracters for performing a subtraction of xe2x80x9c1xe2x80x9d from the number of failure memory cells of the corresponding storage area outputted respectively from said row address failure number counter/memory and said column address failure number counter/memory each time a failure memory cell is read out respectively from said row address failure number counter/memory and column address failure number counter/memory, and setting the result of the subtractions in said row address failure number counter/memory and said column address failure number counter/memory, respectively.
The aforesaid re-starting apparatus comprises: a pair of carry selectors for detecting the facts that the row address signal and column address signal outputted respectively from said row address generator and said column address generator have reached their last addresses, respectively; and a controller receiving carry signals outputted from these carry selectors and performing a control which resumes the incrementing operation of said row address generator or said column address generator having paused in operation.
The aforesaid must-repair search resuming means comprises: control means for performing a control which detects a coincidence between the condition that said must-repair searching apparatus detects the presence of a must-repair on either one of the row address direction or column address direction, and said data updating apparatus operates to update the number of spare line stored in said memory for storing the number of spare lines and the condition that the search operation for a must-repair has completed, and causing a search operation for a must-repair on the one address direction using the updated number of spare line as the detecting condition of a must-repair to be executed.
The aforesaid search ending means comprises: means detecting a completion of two conditions that the address generated from said storage area address generator has reached the last address and that said must-repair searching apparatus has ended the search operation for a must-repair on the row address direction or column address direction without detecting any must-repair.
The method of analyzing a repair of failure cell or cells in a memory and the failure relief analyzer using this analyzing method according to the present invention are characterized in the construction which comprises: a total failure number counter/memory for storing the total number of failure memory cells in each storage area of a memory under test, a spare line number storing memory for storing the number of spare lines provided in the row address direction and in the column address direction, a row address failure number counter/memory and a column address failure number counter/memory for counting the number of failure memory cells occurring at each row address and each column address in each storage area, respectively, and storing them therein, and a must-repair searching apparatus for reading out the number of failures at each address of the row address failure number counter/memory and the column address failure number counter/memory to search a must-repair. By this characterized construction, when the must-repair searching apparatus detects a must-repair, an updating operation for analyzing data can immediately be executed at that address position so that the stored values in each counter/memory can be updated.
Accordingly, in accordance with the present invention, without intervention of the main controller 111, when a must-repair is detected during the search operation of a must-repair, an updating operation of analyzing data is automatically executed. As a result, there is no need to carry out an operation for sequentially setting an address of the detected must-repair and the number of spare line in the failure relief analyzer, and hence the failure relief analysis can be executed in a short time.